1. Field of the Invention
The present invention generally relates to a semiconductor memory device. More particularly, the present invention relates to a data bus structure of the semiconductor memory device having memory arrays arranged so as to surround a peripheral-circuit region located in the center of the chip.
2. Description of the Background Art
Conventionally, dynamic random access memories (DRAMs) including synchronous dynamic random access memories (SDRAMs) generally have a 2n-bit storage capacity. In order to realize this capacity, the memory arrays or banks of the DRAM are generally arranged in two by two, i.e., two rows by two columns.
Developing a new DRAM with a fourfold memory capacity in a 3-year cycle is the conventional trend. However, it is becoming technically difficult to improve the memory capacity as such. In the meantime, with expansion of the information and communication industry such as widespread use of the Internet, there is an active demand on the market for the improved memory capacity. In such circumstances, a DRAM having a 2(2n+1)-bit capacity has also been developed against the conventional trend. Such a DRAM may have an irregular memory-array arrangement instead of the conventional mainstream, i.e., the arrangement in two rows by two columns.
FIG. 14 is a diagram showing an example of the conventional irregular memory-array arrangement.
Referring to FIG. 14, a semiconductor memory device 500 includes four banks A to D. Each of the banks A, B, C and D is formed from a respective one of memory arrays AU, BU, CU and DU corresponding to upper data input/output (I/O) terminals UDQ and a respective one of memory arrays AL, BL, CL and DL corresponding to lower data I/O terminals LDQ. Each memory array has a 64-Mbit capacity, and each bank has a 128-Mbit capacity.
In other words, the banks A, B, C and D respectively include the memory arrays AU, BU, CU and DU corresponding to the upper data I/O terminals.
The banks A, B, C and D further includes the memory arrays AL, BL, CL and DL corresponding to the lower data I/O terminals, respectively.
Due to the shape of a memory cell unit, each memory array having a plurality of memory cells arranged in a matrix is sized to have a shorter side L and a longer side 2L. A column decoder band CPW is provided along one of the shorter sides of each memory array. Each column decoder band CPW includes preamplifiers and write drivers in addition to column decoders. A row decoder band RD is provided along one of the longer sides of each memory array.
The semiconductor memory device 500 is divided into nine regions of three rows by three columns. The memory arrays AL, DU and DL are respectively located in the regions of the first row, first column, the first row, second column, and the first row, third column. The memory arrays AU and CU are respectively located in the regions of the second row, first column, and the second row, third column. The memory arrays BL, BU and CL are respectively located in the regions of the third row, first column, the third row, second column, and the third row, third column.
The region of the second row, second column is the central region CEN. A plurality of pads PD and not-shown peripheral circuitry are provided in the central region CEN. The plurality of pads PD are divided into two pad trains, which are located in parallel with the longer side of the central region CEN. The first train located near the memory array DU includes the pads corresponding to the lower data I/O terminals LDQ. The second train located near the memory array BU includes the pads corresponding to the upper data I/O terminals UDQ.
Note that, in the case where the data I/O terminals for outputting and receiving the data receive 16-bit signals DQ0 to DQ15, the lower data I/O terminals LDQ respectively receive the signals DQ0 to DQ7, and the upper data I/O terminals UDQ respectively receive the signals DQ8 to DQ15.
An example of the simplest data bus structure corresponding to such a memory-array arrangement is shown in FIG. 14. An I/O line within a memory array and a data bus are connected to each other through the preamplifier and the write driver that are included in the corresponding column decoder band CPW provided along the shorter side of the memory array. Therefore, the data bus includes the portions located near the respective column decoder bands CPW and extending in parallel with the shorter side of the chip. These portions are connected to each other so as to allow for the data transmission between these portions and the data I/O terminals.
The total length of the data bus is not sufficiently considered in the conventional memory-array arrangement shown in FIG. 14. More specifically, the semiconductor memory device 500 having the three-row by three-column arrangement shown in FIG. 14 includes a data bus 502 for transmitting the data to the lower data I/O terminals LDQ and a data bus 504 for transmitting the data to the upper data I/O terminals UDQ.
In such a memory-array arrangement, the total length of the data bus 502 is about 8L, provided that the shorter side of the memory array is L. In this case, this data bus has the longest total length. This data bus itself has the largest load, which may significantly degrade the frequency characteristics in the read operation if the semiconductor memory device has short CAS latency in the data transmission. This may also increase the effective data write time, making it difficult to write the data to the memory array at a high speed.
As has been described above, in the irregular memory-array arrangement in which the memory arrays are arranged around the central region, the use of a simple memory-array arrangement or data bus structure is likely to make it difficult to satisfy a required specification.
It is an object of the present invention to provide a semiconductor memory device having a reduced load on a data bus and thus having improved operation frequency characteristics in the case where memory arrays are arranged so as to surround a peripheral-circuit region located in the center of the chip.
In summary, according to the present invention, a semiconductor memory device formed in a memory region of a main surface of a semiconductor substrate includes first and second input/output (I/O) terminal groups, a plurality of first memory blocks, a plurality of second memory blocks, a first data bus, and a second data bus.
The first and second I/O terminal groups are each located collectively in a central region of the memory region. The plurality of first memory blocks are provided in a peripheral region surrounding the central region, for receiving and outputting data from and to the first I/O terminal group. The plurality of second memory blocks are provided in the peripheral region, for receiving and outputting data from and to the second I/O terminal group. The plurality of second memory blocks are each located at a position symmetric to a position of the corresponding first memory block with respect to the central region, and are arranged so as to surround the central region together with the first memory blocks. The first data bus connects the first I/O terminal group to the plurality of first memory blocks. The second data bus connects the second I/O terminal group to the plurality of second memory blocks.
According to another aspect of the present invention, a semiconductor memory device formed in a memory region of a main surface of a semiconductor substrate includes first and second input/output (I/O) terminal groups, a plurality of first memory blocks, a plurality of second memory blocks, a first data bus, a second data bus, and a selection circuit.
The first and second I/O terminal groups are each located collectively in a central region of the memory region. The plurality of first memory blocks are provided in a peripheral region surrounding the central region, for receiving and outputting data from and to the first I/O terminal group. The plurality of second memory blocks are provided in the peripheral region, for receiving and outputting data from and to the second I/O terminal group. The plurality of second memory blocks are arranged so as to surround the central region together with the first memory blocks. The first data bus connects the first I/O terminal group to the plurality of first memory blocks. The second data bus connects the second I/O terminal group to the plurality of second memory blocks. The second data bus includes a first sub data bus for transmitting data to and from one of the plurality of second memory blocks, and a second sub data bus for transmitting data to and from another one of the plurality of second memory blocks. The selection circuit is provided in the central region, for selecting one of the first and second sub data buses according to an address signal so as to transmit data to and from the second I/O terminal group.
Accordingly, a main advantage of the present invention is that, in an irregular memory-array arrangement in which the memory arrays are arranged so as to surround the central region, the total length of the data bus can be reduced, allowing for high-speed data transmission.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.